Fundamental goals in a digital receiver for a digital communication system are to minimize the amount of received power required in order to achieve a given bit error rate (BER), and to maximize the data throughput (achieve maximum bandwidth). For example, in an optical fiber communication system, each receiver includes a photodetector which detects the incident light signal with its data encoding and converts it into a small electrical current. A low-noise amplifier or preamplifier following the photodetector amplifies the photodetector current to produce a usable signal while introducing a minimum amount of excess noise. The signal at the output of the amplifier is applied to a digital regenerator or bit decision circuit (also sometimes known as a slicer) in order to determine at each moment whether a logic zero (logic low) or a logic one (logic high) is being received. The bit decision circuit is basically a comparator which compares the instantaneous value of the signal voltage with a threshold voltage representing the transition between a logic low level and a logic high level, and establishes the logic level depending upon whether the signal voltage is high or low relative to the threshold voltage.
It may be desirable to ac (alternating-current) couple the signal from the photodiode or other detector to the data decision circuit. The term "ac" applies not only to current but also to voltages which alternate about a reference value, and the term "ac coupling" or "ac coupled" refers to a signal condition in which the deviation of the peak values of the voltage or current from the reference value depends upon the average value of the signal itself, which condition may be achieved by passing the signal through a circuit which does not respond to direct current, such as a series capacitor or a transformer. Such ac coupling may be desirable, for example, in order to simplify the design of the preamplifier. When the signal is ac coupled, it is possible to introduce errors into the data decision process which are attributable to changes in the average value of the digitial signal which result from duty cycle changes of the signal. The duty cycle changes in turn result from the different patterns of logic ones and logic zeroes which carry the message information.
It is possible to select data codes which eliminate direct and low-frequency components of the signal. With the direct components elminated from the signal, the signal received by the detector may be ac coupled to the bit decision circuit without perturbations attributable to signal information content. However, when very high data rates are involved, the use of such specialized coding may not be cost-effective, because increased channel bandwidth is required.
In a burst mode system such as a local area network system, it may not be possible to maintain constant duty cycle. Even if each burst or packet of data individually has constant duty cycle, their indeterminate times of arrival may result in variations of the signal baseline.
As the bandwidth of the data signal is increased, fewer bit decision circuits are available which operate reliably at the signal frequencies corresponding to the upper end of the signal bandwidth. At the current state of the art, bit decisions are reliably made at signal frequencies approaching 1.1 GHz by gallium arsenide (GaAs) OR or NOR integrated circuit gates. These gates are of the ECL (emitter coupled logic) types, which are adapted to receive signal in a voltage range extending from about zero volts to approximately-2.6 volts. The OR/NOR gates compare the magnitude of the received signal with an internally generated threshold voltage, which has a value of approximately -1.3 volts. When it is desired to use such a gate as a data decision circuit, variations in the duty cycle of the signal pulses may cause average value perturbations which affect the reliability of the data decisions if the signal is ac coupled. It is desired to use logic gates with internal thresholds to make bit decision, and to ac couple signal from the detector to the logic gate.